丝印：874；Package：16Ld2.6x1.8UTQFN；PWM DC/DC Controllers with VID Inputs for Portable GPU Core-Voltage Regulator

文件：1.281 Mbytes 页数：29 Pages

RENESAS

瑞萨

丝印：87421AIL；Package：SOIC；÷1/÷2 Differential-to-LVDS Clock Generator

FEATURES • One differential LVDS output • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS

文件：408.84 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：87421AIL；Package：SOIC；÷1/÷2 Differential-to-LVDS Clock Generator

FEATURES • One differential LVDS output • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS

文件：408.84 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：874B；Package：VFQFN；1:2 Different ial-to-LVPECL Buffer/Divider

文件：366.72 Kbytes 页数：20 Pages

IDT

丝印：874B；Package：VFQFN；1:2 Different ial-to-LVPECL Buffer/Divider

文件：366.72 Kbytes 页数：20 Pages

IDT

丝印：8742H；Package：TQFP；HART and FOUNDATION Fieldbus / PROFIBUS PA Modems

文件：259.92 Kbytes 页数：11 Pages

TI

德州仪器

丝印：8742H；Package：TQFP；DAC874xH, HART and FOUNDATION Fieldbus / PROFIBUS PA Modems

文件：1.84393 Mbytes 页数：53 Pages

TI

德州仪器

丝印：8742H；Package：TQFP；DAC874xH, HART and FOUNDATION Fieldbus / PROFIBUS PA Modems

文件：1.84393 Mbytes 页数：53 Pages

TI

德州仪器

丝印：ICS8741004BIL；Package：TSSOP；Differential-to-LVDS/0.7V Differential PCI Express™ Jitter Attenuator

Features • Two LVDS and two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs • One differential clock input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output fr

文件：633.46 Kbytes 页数：23 Pages

RENESAS

瑞萨

丝印：ICS8741004BIL；Package：TSSOP；Differential-to-LVDS/0.7V Differential PCI Express™ Jitter Attenuator

Features • Two LVDS and two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs • One differential clock input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output fr

文件：633.46 Kbytes 页数：23 Pages

RENESAS

瑞萨