8731-01中文资料瑞萨数据手册PDF规格书

FEATURES

• Eleven differential 3.3V LVPECL outputs

• Differential reference clock input pair

• REF_CLK, nREF_CLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Maximum output frequency: 700MHz

• Maximum reference clock input frequency: 200MHz

• VCO range: 250MHz - 700MHz

• Accepts any single-ended input signal with a resistor bias

on nCLK input

• External feedback for zero delay capabilitiy

• Output skew: 70ps (maximum)

• Cycle-to-cycle jitter: 65ps (maximum)

• Full 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Available in lead-free RoHS compliant package