8725BY-01LF集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

特性 Features

• Five differential HSTL output pairs

• Selectable differential CLKx/nCLKx input pairs

• CLKx/nCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, HSTL, HCSL, SSTL

• Output frequency range: 31.25MHz to 700MHz

• Input frequency range: 31.25MHz to 700MHz

• VCO range: 250MHz to 700MHz

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Static phase offset: 15ps ± 135ps

• Cycle-to-cycle jitter: 25ps (maximum)

• Output skew: 45ps (maximum)

• 3.3V core, 1.8V output operating supply

• 0°C to 70°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages