8701中文资料瑞萨数据手册PDF规格书

FEATURES

• Twenty LVCMOS outputs, 7Ω typical output impedance

• One LVCMOS/LVTTL clock input

• Maximum output frequency: 250MHz

• Bank enable logic allows unused banks to be disabled

in reduced fanout applications

• Output skew: 250ps (maximum)

• Part-to-part skew: 600ps (maximum)

• Bank skew: 200ps (maximum)

• Multiple frequency skew: 300ps (maximum)

• 3.3V or mixed 3.3V input, 2.5V output operating

supply modes

• 0°C to 70°C ambient operating temperature

• Other divide values available on request

• Available in lead-free RoHS compliant package