Customer Specification

Construction 1) Component 1 4 X 1 COND a) Conductor 24 (7/32) AWG Bare Copper 0.024 b) Insulation 0.016 Wall, Nom. TPES(Hytrel) 0.056 (1) Print ALPHANUMERIC NUMBERS - 1-ONE ALTERNATING AND INVERTED (2) Color Code Alpha Wire Color Code KX Cond Color Cond Color Cond Color 1 GREEN/YELL

文件：98.88 Kbytes 页数：4 Pages

ALPHAWIRE

1:4, Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator

The 87004 is a highly versatile 1:4 Differentialto- LVCMOS/LVTTL Clock Generator and a member of the HiPerClockS® family of High Performance Clock Solutions from IDT. The 87004 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. • Four LVCMOS/LVTTL outputs, 7? typical output impedance\n• Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs\n• CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\n• Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CLK0 and CLK1 in;

Renesas

瑞萨

包装：散装 类别：标签，标志，护栏，标识 标签 描述：B851 5.75HX3 BK/RD/WH 2-SIDE REV

Brady Corporation

包装：散装 类别：标签，标志，护栏，标识 标签 描述：B851 5.75HX3 BK/RD/WH 2-SIDE REV

Brady Corporation

丝印：ICS87004AG；Package：TSSOP；1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

文件：829.71 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS87004AGLF；Package：TSSOP；1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

文件：829.71 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS87004AGLF；Package：TSSOP；1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

文件：829.71 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS87004AG；Package：TSSOP；1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

文件：829.71 Kbytes 页数：16 Pages

RENESAS

瑞萨

LVCMOS/LVTTL FANOUT BUFFER/DIVIDER Maximum output frequency: 250MHz

GENERAL DESCRIPTION The ICS87004I-03 is a low skew, ÷1, ÷2 ÷3, ÷4 ÷5, ÷6 ÷8, ÷16 LVCMOS/LVTTL Fanout Buffer/Divider and a member of theHiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS87004I-03 has selectable clock inputs that accept single ended input levels. Output enabl

文件：254.77 Kbytes 页数：12 Pages

IDT

LVCMOS/LVTTL FANOUT BUFFER/DIVIDER Maximum output frequency: 250MHz

GENERAL DESCRIPTION The ICS87004I-03 is a low skew, ÷1, ÷2 ÷3, ÷4 ÷5, ÷6 ÷8, ÷16 LVCMOS/LVTTL Fanout Buffer/Divider and a member of theHiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS87004I-03 has selectable clock inputs that accept single ended input levels. Output enabl

文件：254.77 Kbytes 页数：12 Pages

IDT