8600V数据手册Lattice中文资料规格书

描述 Description

The ispLSI 8000V Family of Register-Intensive, 3.3V SuperBIG In-System Programmable Logic Devices is based on Big Fast Megablocks of 120 registered macrocells and a Global Routing Plane (GRP) structure interconnecting the Big Fast Megablocks. Each Big Fast Megablock contains 120 registered macrocells arranged in six groups of 20, a group of 20 being referred to as a Generic Logic Block, or GLB. Within the Big Fast Megablock, a Big Fast Megablock Routing Pool (BRP) interconnects the six GLBs to each other and to 24 Big Fast Megablock I/O cells with optional I/O registers.

特性 Features

• SuperBIG HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC
— 3.3V Power Supply
— 32,000 PLD Gates/600 Macrocells
— 192-264 I/O Pins Supporting 3.3V/2.5V I/O
— 864 Registers
— High-Speed Global and Big Fast Megablock (BFM) Interconnect
— Wide 20-Macrocell Generic Logic Block (GLB) for High Performance
— Wide Input Gating (44 Inputs per GLB) for Fast Counters, State Machines, Address Decoders, Etc.
— PCB-Efficient Ball Grid Array (BGA) Package Options
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 8.5 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE