854S054I中文资料4:1 Differential-to-LVDS Clock Multiplexer数据手册Renesas规格书

描述 Description

The 854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.5GHz. The 854S054I has 4 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS or CML levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0).

特性 Features

• High speed 4:1 differential multiplexer
• One differential LVDS output pair
• Four selectable differential PCLK, nPCLK input pairs
• PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML
• Maximum output frequency: 2.5GHz
• Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input
• Additive phase jitter, RMS: 0.147ps (typical)
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 700ps (maximum)
• Supply voltage range: 3.135V to 3.465V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package