85408I中文资料Low Skew,1-to-8,Differential-to-LVDS Clock数据手册Renesas规格书

描述 Description

The 85408I is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the family of High Performance Clock Solutions from IDT. The 85408I CLK, nCLK pair can accept most differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the 85408I provides a low power, low noise, low skew, point-to-point solution for distributing LVDS clock signals. Guaranteed output and part-to-part skew specifications make the 85408I ideal for those applications demanding well defined performance and repeatability.

特性 Features

• Eight differential LVDS output pairs
• CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks
• Multiple output enable inputs for disabling unused outputs in reduced fanout applications
• Output skew: 50ps (maximum)
• Propagation delay: 2.4ns (maximum)
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package