| 型号 | 下载 订购 | 功能描述 | 制造商 上传企业 | LOGO |
|---|---|---|---|---|
2:1 Differential-to-LVPECL Multiplexer Features • One LVPECL output pair • Two selectable differential LVPECL clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx • Part- 文件：683.3 Kbytes 页数：24 Pages | RENESAS 瑞萨 | RENESAS | ||
Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le 文件：848.25 Kbytes 页数：21 Pages | RENESAS 瑞萨 | RENESAS | ||
丝印：1BIL；Package：TSSOP；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le 文件：848.25 Kbytes 页数：21 Pages | RENESAS 瑞萨 | RENESAS | ||
丝印：1BIL；Package：TSSOP；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le 文件：848.25 Kbytes 页数：21 Pages | RENESAS 瑞萨 | RENESAS | ||
丝印：3S011BIL；Package：SOIC；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le 文件：848.25 Kbytes 页数：21 Pages | RENESAS 瑞萨 | RENESAS | ||
丝印：3S011BIL；Package：SOIC；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le 文件：848.25 Kbytes 页数：21 Pages | RENESAS 瑞萨 | RENESAS | ||
丝印：ICS3S012AIL；Package：VFQFN；12:1, Differential-to-3.3V, 2.5V LVPECL Clock/Data Multiplexer Features • High speed 12:1 differential multiplexer • One differential 3.3V or 2.5V LVPECL output • Twelve selectable differential clock or data inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output frequency: 3.2GHz • Translates a 文件：1.030609 Mbytes 页数：21 Pages | RENESAS 瑞萨 | RENESAS | ||
丝印：ICS3S012AIL；Package：VFQFN；12:1, Differential-to-3.3V, 2.5V LVPECL Clock/Data Multiplexer Features • High speed 12:1 differential multiplexer • One differential 3.3V or 2.5V LVPECL output • Twelve selectable differential clock or data inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output frequency: 3.2GHz • Translates a 文件：1.030609 Mbytes 页数：21 Pages | RENESAS 瑞萨 | RENESAS | ||
丝印：53S01AIL；Package：TSSOP；2:1 Differential-to-LVPECL Multiplexer Features • One LVPECL output pair • Two selectable differential LVPECL clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx • Part- 文件：683.3 Kbytes 页数：24 Pages | RENESAS 瑞萨 | RENESAS | ||
丝印：53S01AIL；Package：TSSOP；2:1 Differential-to-LVPECL Multiplexer Features • One LVPECL output pair • Two selectable differential LVPECL clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx • Part- 文件：683.3 Kbytes 页数：24 Pages | RENESAS 瑞萨 | RENESAS |
详细参数
- 型号：
853S
- 功能描述：
时钟缓冲器
- 1：
2 LVPECL/ECL Fanout Buffer
- RoHS：
否
- 制造商：
Texas Instruments
- 输出端数量：
5
- 最大输入频率：
40 MHz
- 电源电压-最大：
3.45 V
- 电源电压-最小：
2.375 V
- 最大工作温度：
+ 85 C
- 最小工作温度：
- 40 C
- 封装/箱体：
LLP-24
- 封装：
Reel
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
IDT |
24+ |
原厂封装 |
2000 |
原装现货假一罚十 |
询价 | ||
IDT |
三年内 |
1983 |
只做原装正品 |
询价 | |||
24+ |
TSSOP8 |
20000 |
全新原厂原装，进口正品现货，正规渠道可含税！！ |
询价 | |||
IDT, Integrated Device Technol |
24+ |
20-SOIC |
56200 |
一级代理/放心采购 |
询价 | ||
IDT |
23+ |
NA |
320 |
原装正品代理渠道价格优势 |
询价 | ||
IDT |
1931+ |
N/A |
1186 |
加我qq或微信，了解更多详细信息,体验一站式购物 |
询价 | ||
RENESAS(瑞萨)/IDT |
2447 |
TSSOP-16 |
315000 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
询价 | ||
IDT |
25+ |
SSOP-8 |
932 |
就找我吧!--邀您体验愉快问购元件! |
询价 | ||
Renesas |
25+ |
25000 |
原厂原包 深圳现货 主打品牌 假一赔百 可开票! |
询价 | |||
RENESAS(瑞萨)/IDT |
2021+ |
SOIC-8 |
499 |
询价 |
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