8533-01中文资料Low Skew,1-to-4 Differential-to-3.3V LVPECL Fanout Buffer数据手册Renesas规格书

描述 Description

The 8533-01 is a low skew, high performance 1-to-4 Differential-to-3.3V LVPECL Fanout Buffer. The 8533- 01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8533-01 ideal for those applications demanding well defined performance and repeatability.

特性 Features

Four differential 3.3V LVPECL outputs
Selectable differential CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
Maximum output frequency: 650MHz
Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input
Output skew: 30ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 1.4ns (maximum)
Additive phase jitter, RMS: 0.06ps (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Lead-Free packages available
Industrial temperature information available upon request