841654I数据手册Renesas中文资料规格书

描述 Description

The 841654I is an optimized PCIe and sRIO clock generator and member of the family of high-performance clock solutions from IDT. The device uses a 25MHz parallel crystal to generate 100MHz and 125MHz clock signals, replacing solutions requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter PCIe or sRIO or both clock signals. Designed for telecom, networking and industrial applications, the 841654I can also drive the high-speed sRIO and PCIe SerDes clock inputs of communication processors, DSPs, switches and bridges.

特性 Features

·Four differential HCSL clock outputs: configurable for PCIe (100MHz) and sRIO (100MHz or 125MHz) clock signals One REF_OUT LVCMOS/LVTTL clock output
·Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference clock input
·Supports the following output frequencies:100MHz or 125MHz
·VCO: 500MHz
·PLL bypass and output enable
·RMS phase jitter at 100MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.44ps (typical)
·Full 3.3V power supply mode
·-40°C to 85°C ambient operating temperature
·Available in lead-free (RoHS 6) package