8344BYILF集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

FEATURES

• Twenty-four LVCMOS/LVTTL outputs,

7Ω typical output impedance

• Two selectable differential clock input pairs for redundant

clock applications

• CLKx, nCLKx pair can accept the following differential

input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

• Maximum output frequency: 100MHz

• Translates any single-ended input signal to LVCMOS/LVTTL

with resistor bias on nCLK input

• Multiple output enable pins for disabling unused outputs

in reduced fanout applications

• Output skew: 275ps (maximum)

• Part-to-part skew: 600ps (maximum)

• Bank skew: 150ps (maximum)

• Supply modes:

Core/Output

3.3V/3.3V

3.3V/2.5V

2.5V/2.5V

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package