Low Skew, 1-TO-16 LVCMOS/LVTTL Fanout Buffer

Features • Sixteen LVCMOS / LVTTL outputs, 15 output impedance • One LVCMOS / LVTTL clock input • Maximum output frequency: 200MHz • All inputs are 5V tolerant • Output skew: 250ps (maximum) • Part-to-part skew: 800ps (maximum) • Additive phase jitter, RMS: 0.09ps (typical) • Full 3.3V op

文件：354.15 Kbytes 页数：12 Pages

RENESAS

瑞萨

Low Skew, 1-TO-16 LVCMOS/LVTTL Fanout Buffer

文件：161.81 Kbytes 页数：11 Pages

IDT

Low Skew,1-to-16,LVCMOS/LVTTL Fanout Buffer

The 83115 is a low skew, 1-to-16 LVCMOS/ LVTTL Fanout Buffer. The 83115 single-ended clock input accepts LVCMOS or LVTTL input levels. The 83115 operates at full 3.3V supply mode over the commercial temperature range. Guaranteed output and part-to-part skew characteristics make the 83115 ideal for t ·Sixteen LVCMOS / LVTTL outputs, 15Ω output impedance\n·One LVCMOS / LVTTL clock input\n·Maximum output frequency: 200MHz\n·All inputs are 5V tolerant\n·Output skew: 250ps (maximum)\n·Part-to-part skew: 800ps (maximum)\n·Additive phase jitter, RMS: 0.09ps (typical)\n·Full 3.3V operating supply\n·0°C;

Renesas

瑞萨

包装：散装 类别：工具 配件 描述：TRAY UNV PARTS RECT

ATG

丝印：83115BRILF；Package：SSOP；Low Skew, 1-to-16 LVCMOS/LVTTL Fanout Buffer

Features • Sixteen LVCMOS / LVTTL outputs, 15 output impedance • One LVCMOS / LVTTL clock input • Maximum output frequency: 200MHz • All inputs are 5V tolerant • Output skew: 250ps (maximum) • Part-to-part skew: 800ps (maximum) • Additive phase jitter, RMS: 0.20ps (typical) • Full 3.3V op

文件：353.37 Kbytes 页数：12 Pages

RENESAS

瑞萨

丝印：83115BRILF；Package：SSOP；Low Skew, 1-to-16 LVCMOS/LVTTL Fanout Buffer

Features • Sixteen LVCMOS / LVTTL outputs, 15 output impedance • One LVCMOS / LVTTL clock input • Maximum output frequency: 200MHz • All inputs are 5V tolerant • Output skew: 250ps (maximum) • Part-to-part skew: 800ps (maximum) • Additive phase jitter, RMS: 0.20ps (typical) • Full 3.3V op

文件：353.37 Kbytes 页数：12 Pages

RENESAS

瑞萨

Low Skew, 1-to-16 LVCMOS/LVTTL Fanout Buffer

Features • Sixteen LVCMOS / LVTTL outputs, 15 output impedance • One LVCMOS / LVTTL clock input • Maximum output frequency: 200MHz • All inputs are 5V tolerant • Output skew: 250ps (maximum) • Part-to-part skew: 800ps (maximum) • Additive phase jitter, RMS: 0.20ps (typical) • Full 3.3V op

文件：353.37 Kbytes 页数：12 Pages

RENESAS

瑞萨

Between Series Adapters

文件：378.71 Kbytes 页数：6 Pages

WINCHESTER

温彻斯特

丝印：83115BRILF；Package：SSOP；Low Skew, 1-to-16 LVCMOS/LVTTL Fanout Buffer

文件：161.03 Kbytes 页数：11 Pages

IDT

丝印：83115BRILF；Package：SSOP；Low Skew, 1-to-16 LVCMOS/LVTTL Fanout Buffer

文件：161.03 Kbytes 页数：11 Pages

IDT