Features

• Differential reference inputs (IN1 to IN4) accept clock frequencies

between 1 PPS and 650 MHz

• Single ended inputs (IN5 to IN6) accept reference clock frequencies

between 1 PPS and 162.5 MHz

• Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any

clock reference input

• Reference monitors qualify/disqualify references depending on activity, frequency and LOS pins

• Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables,

revertive and non-revertive settings and other programmable settings

• Fractional-N input dividers enable the DPLLs to lock to a wide range

of reference clock frequencies including: 10/100/1000 Ethernet, 10G

Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI, and GNSS frequencies

• Any reference inputs (IN1 to IN6) can be designated as external sync

pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a selectable reference clock input

• FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses

that are aligned with the selected external input sync pulse input and

frequency locked to the associated reference clock input

• DPLL1 can be configured with bandwidths between 0.09 mHz and

567 Hz

• DPLL1 locks to input references with frequencies between 1 PPS and

650 MHz

• DPLL2 locks to input references with frequencies between 8 kHz and

650 MHz

• DPLL1 complies with ITU-T G.8262 for Synchronous Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equipment Clock

(SEC); and Telcordia GR-253-CORE/ GR-1244-CORE for Stratum 3

and SONET Minimum Clock (SMC)

• DPLL1 generates clocks with PDH, TDM, GSM, CPRI/OBSAI, 10/100/

1000 Ethernet and GNSS frequencies; these clocks are directly available on OUT1 and OUT8

• DPLL2 generates N x 8 kHz clocks up to 100 MHz that are output on

OUT9 and OUT10

• APLL1 and APLL2 are connected to DPLL1

• APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or

SONET/SDH frequencies

• Any of eight common TCXO/OCXO frequencies can be used for the

System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz,

24.576 MHz, 25 MHz or 30.72 MHz

• The I2C slave, SPI or the UART interface can be used by a host processor to access the control and status registers

• The I2C master interface can automatically load a device configuration from an external EEPROM after reset

• Differential outputs OUT3 to OUT6 output clocks with frequencies

between 1 PPS and 650 MHz

• Single ended outputs OUT1, OUT2, OUT7 and OUT8 output clocks

with frequencies between 1 PPS and 125 MHz

• Single ended outputs OUT9 and OUT10 output clocks N*8 kHz multiples up to 100 MHz

• DPLL1 supports independent programmable delays for each of IN1 to

IN6; the delay for each input is programmable in steps of 0.61 ns with

a range of ~±78 ns

• The input to output phase delay of DPLL1 is programmable in steps of

0.0745 ps with a total range of ±20 s

• The clock phase of each of the output dividers for OUT1 (from APLL1)

to OUT8 is individually programmable in steps of ~200 ps with a total

range of +/-180°

• 1149.1 JTAG Boundary Scan

• 72-QFN green package

Description

The 82P33714 Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE) provides tools to manage timing references,

clock generation and timing paths for SyncE based clocks, per ITU-T G.8264 and ITU-T G.8262. 82P33714 meets the requirements of ITU-T G.8262

for synchronous Ethernet Equipment Clocks (EECs) and ITU-T G.813 for Synchronous Equipment Clocks (SEC). The device outputs low-jitter clocks

that can directly synchronize Ethernet interfaces; as well as SONET/SDH and PDH interfaces.

The 82P33714 accepts four differential reference inputs and two single ended reference inputs that can operate at common GNSS, Ethernet,

SONET/SDH and PDH frequencies that range from 1 Pulse Per Second (PPS) to 650 MHz. The references are continually monitored for loss of signal and for frequency offset per user programmed thresholds. All of the references are available to both Digital PLLs (DPLLs). The active reference for

each DPLL is determined by forced selection or by automatic selection based on user programmed priorities and locking allowances and based on

the reference monitors and LOS inputs.

The 82P33714 can accept a clock reference and an associated phase locked sync signal as a pair. DPLL1 can lock to the clock reference and

align the frame sync and multi-frame sync outputs with the paired sync input. The device allows any of the differential or single ended reference inputs

to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. The input sync signals can

have a frequency of 1 PPS, 2 kHz, 4 kHz or 8 kHz. This feature enables DPLL1 to phase align its frame sync and multi-frame sync outputs with a sync

input without the need use a low bandwidth setting to lock directly to the sync input.

The DPLLs support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode the DPLLs synthesize clocks based on

the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term output frequency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL uses frequency data

acquired while in Locked mode to generate accurate frequencies when input references are not available.

DPLL1 also supports DCO mode. In DCO mode the DPLL control loop is opened and the DCO can be controlled by an IEEE 1588 clock recovery

servo running on an external processor to synthesize IEEE 1588 clocks.

The 82P33714 requires a system clock for its reference monitors and other digital circuitry. The frequency accuracy of the system clock determines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequency stability of the

DPLLs in Free-Run mode and in Holdover mode; and it affects the wander generation of the DPLLs in Locked mode.

When used with a suitable system clock, DPLL1 meets the frequency accuracy, pull-in, hold-in, pullout, noise generation, noise tolerance, transient response, and holdover performance requirements of the following applications: ITU-T G.8262/G.813 EEC/SEC options 1 and 2, Telcordia GR1244 Stratum 3 (S3), Telcordia GR-253-CORE S3 and SONET Minimum Clock (SMC).

DPLL1 can be configured with a range of selectable filtering bandwidths from 0.09 MHz to 567 Hz. The 17 MHz bandwidth can be used to lock the

DPLL directly to a 1 PPS reference. The 92 MHz bandwidth can be used for G.8262/G.813 Option 2, or Telcordia GR-253-CORE S3, or SMC applications. The bandwidths in the range 1.1 Hz to 8.9 Hz can be used for G.8262/G.813 Option 1 applications. The bandwidth of 1.1 Hz or 2.2 Hz can be

used for Telcordia GR-1244-CORE S3 applications. Bandwidths above 10 Hz can be used in jitter attenuation and rate conversion applications.

DPLL2 is a wideband (BW > 25Hz) frequency translator that can be used, for example, to convert a recovered line clock to a 1.544 MHz or 2.048

MHz synchronization interface clock.

For SETS applications per ITU-T G.8264, DPLL1 is configured as an EEC/SEC to output clocks for the T0 reference point and DPLL2 is used to

output clocks for the T4 reference point.

Clocks generated by DPLL1 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The output

clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces.

All 82P33714 control and status registers are accessed through an I2C slave, SPI or UART interface. For configuring the DPLLs, APLL1 and

APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset.

82P33714属于集成电路（IC） > 应用特定时钟/定时。瑞萨科技有限公司制造生产的82P33714应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。