82801DB中文资料英特尔数据手册PDF规格书

I/O Controller Hub 4 (ICH4)

Intel® 82801DB ICH4 Features

■ PCI Bus Interface

— Supports PCI Revision 2.2 Specification at 33 MHz

— 133 MB/sec maximum throughput

— Supports up to six master devices on PCI

— One PCI REQ/GNT pair can be given higher arbitration priority (intended for external 1394 host controller)

— Support for 44-bit addressing on PCI using DAC protocol

■ Integrated LAN Controller

— WfM 2.0 and IEEE 802.3 compliant

— LAN Connect Interface (LCI)

— 10/100 Mbit/sec ethernet support

■ Integrated IDE Controller

— Supports “Native Mode” register and interrupts

— Independent timing of up to 4 drives, with separate primary and secondary IDE cable connections

— Ultra ATA/100/66/33, BMIDE and PIO modes

— Tri-state modes to enable swap bay

■ USB

— Includes three UHCI host controllers that support six external ports

— New: Includes one EHCI high-speed USB 2.0 Host Controller that supports all six ports

— New: Supports a USB 2.0 high-speed debug port

— Supports wake-up from sleeping states S1–S5

— Supports legacy keyboard/mouse software

■ AC-Link for Audio and Telephony CODECs

—Supports AC ’97 2.3

— New: Third AC_SDATA_IN line for three codec support

— New: Independent bus master logic for seven channels (PCM In/Out, Mic 1 input, Mic 2 input, modem in/out, S/PDIF out)

— Separate independent PCI functions for audio and modem

— Support for up to six channels of PCM audio output (full AC3 decode)

— Supports wake-up events

■ Interrupt Controller

— Support up to eight PCI interrupt pins

— Supports PCI 2.2 message signaled interrupts

— Two cascaded 82C59 with 15 interrupts

— Integrated I/O APIC capability with 24 interrupts

— Supports serial interrupt protocol

— Supports processor system bus interrupt delivery

■ New: 1.5 V operation with 3.3 V I/O

— 5 V tolerant buffers on IDE, PCI, USB over current and legacy signals

■ Timers Based on 82C54

— System timer, refresh request, speaker tone output

■ Power Management Logic

— ACPI 2.0 compliant

— ACPI-defined power states (C1–C2, S3–S5 )

— Supports Desktop S1 state (like C2 state, only STPCLK# active)

— ACPI power management timer

— PCI PME# support

— SMI# generation

— All registers readable/restorable for proper resume from 0 V suspend states

■ External Glue Integration

— Integrated pull-up, pull-down and series termination resistors on IDE, processor interface

— Integrated Pull-down and Series resistors on USB

■ Enhanced Hub Interface Buffers Improve Routing flexibility (Not available with all Memory Controller Hubs)

■ Firmware Hub (FWH) Interface Supports BIOS memory size up to 8 MB

■ Low Pin Count (LPC) Interface

— Supports two Master/DMA devices.

■ Enhanced DMA Controller

— Two cascaded 8237 DMA controllers

— PCI DMA: Supports PC/PCI — Includes two PC/PCI REQ#/GNT# pairs

— Supports LPC DMA

— Supports DMA collection buffer to provide Type-F DMA performance for all DMA channels

■ Real-Time Clock

— 256-byte battery-backed CMOS RAM

■ System TCO Reduction Circuits

— Timers to generate SMI# and Reset upon detection of system hang

— Timers to detect improper processor reset

— Supports ability to disable external devices

■ SMBus

— New: Hardware packet error checking

— New: Supports SMBus 2.0 Specification

— Host interface allows processor to communicate via SMBus

— Slave interface allows an external microcontroller to access system resources

— Compatible with most 2-wire components that are also I2C compatible

■ GPIO

— TTL, open-drain, inversion

■ Package 31x31 mm 421 BGA