DESCRIPTION

The 74VHCT373A is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE).

While the LE inputs is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.

Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 6.4 ns (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION:

ICC = 4 µA (MAX.) at TA=25°C

■ COMPATIBLE WITH TTL OUTPUTS:

VIH = 2V (MIN.), VIL = 0.8V (MAX)

■ POWER DOWN PROTECTION ON INPUTS & OUTPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8 mA (MIN)

■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL

■ OPERATING VOLTAGE RANGE:

VCC(OPR) = 4.5V to 5.5V

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373

■ IMPROVED LATCH-UP IMMUNITY

■ LOW NOISE: VOLP = 0.9V (MAX.)

74VHCT373AT属于集成电路（IC） > 锁存器。意法半导体（ST）集团制造生产的74VHCT373AT锁存器锁存器是类似于触发器的基本数字存储设备，但是不同之处在于，在锁存使能（或类似命名）信号处于有效逻辑状态的任何时间，保持的逻辑状态都可以改变。“透明”锁存器还允许设备输出在锁存使能信号有效时反映输入的当前状态，而相反的是，状态仅在保持状态已固定时改变。