Low Voltage 16-Bit Inverting Buffer/Line Driver with Bushold

General Description The VCXH16240 contains sixteen inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorte

文件：76.95 Kbytes 页数：7 Pages

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Low?뭋oltage 1.8/2.5/3.3V 16?묪it Buffer

Low−Voltage 1.8/2.5/3.3V 16−Bit Buffer With 3.6 V −Tolerant Inputs and Outputs (3−State, Inverting) The 74VCXH16240 is an advanced performance, inverting 16−bit buffer. It is designed for very high−speed, very low−power operation in 1.8 V, 2.5 V or 3.3 V systems. When operating at 2.5 V (or 1.8

文件：236.48 Kbytes 页数：11 Pages

ONSEMI

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Low-Voltage 1.8/2.5/3.3V 16-Bit Buffer

ONSEMI

安森美半导体

Low?뭋oltage 1.8/2.5/3.3V 16?묪it Buffer

Low−Voltage 1.8/2.5/3.3V 16−Bit Buffer With 3.6 V −Tolerant Inputs and Outputs (3−State, Inverting) The 74VCXH16240 is an advanced performance, inverting 16−bit buffer. It is designed for very high−speed, very low−power operation in 1.8 V, 2.5 V or 3.3 V systems. When operating at 2.5 V (or 1.8

文件：236.48 Kbytes 页数：11 Pages

ONSEMI

安森美半导体

Low?뭋oltage 1.8/2.5/3.3V 16?묪it Buffer

Low−Voltage 1.8/2.5/3.3V 16−Bit Buffer With 3.6 V −Tolerant Inputs and Outputs (3−State, Inverting) The 74VCXH16240 is an advanced performance, inverting 16−bit buffer. It is designed for very high−speed, very low−power operation in 1.8 V, 2.5 V or 3.3 V systems. When operating at 2.5 V (or 1.8

文件：236.48 Kbytes 页数：11 Pages

ONSEMI

安森美半导体

Low Voltage 16-Bit Inverting Buffer/Line Driver with Bushold

General Description The VCXH16240 contains sixteen inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorte

文件：76.95 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

LOW VOLTAGE CMOS 16-BIT BUFFER (3-STATE INV.) WITH 3.6V TOLERANT INPUTS AND OUTPUTS

ST

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