74V1T02S中文资料意法半导体数据手册PDF规格书

DESCRIPTION

The 74V1T02 is an advanced high-speed CMOS SINGLE 2-INPUT NOR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output.

Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

■ HIGH SPEED: tPD = 5.1ns (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C

■ COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX)

■ POWER DOWN PROTECTION ON INPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) at VCC = 4.5V

■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL

■ OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V

■ IMPROVED LATCH-UP IMMUNITY