General Description

The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in a high impedance state.

Features

■ Input and output interface capability to systems at 5V VCC

■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH373), also available without bushold feature (74LVT373)

■ Live insertion/extraction permitted

■ Power Up/Down high impedance provides glitch-free bus loading

■ Outputs source/sink –32 mA/+64 mA

■ Functionally compatible with the 74 series 373

■ ESD performance:

– Human-body model > 2000V

– Machine model > 200V

– Charged-device model > 1000V

74LVTH373SJ属于集成电路（IC） > 锁存器。安森美半导体公司制造生产的74LVTH373SJ锁存器锁存器是类似于触发器的基本数字存储设备，但是不同之处在于，在锁存使能（或类似命名）信号处于有效逻辑状态的任何时间，保持的逻辑状态都可以改变。“透明”锁存器还允许设备输出在锁存使能信号有效时反映输入的当前状态，而相反的是，状态仅在保持状态已固定时改变。