74LVT16240数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

General Description
The LVT16240 and LVTH16240 contain sixteen inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/receiver. The device is nibble controlled.
Individual 3-STATE control inputs can be shorted together for 8-bit or 16-bit operation.
The LVTH16240 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.
These buffers and line drivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16240 and LVTH16240 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.

特性 Features

■ Input and output interface capability to systems at 5V VCC
■ Bushold data inputs eliminate the need for external
   pull-up resistors to hold unused inputs (74LVTH16240),
   also available without bushold feature (74LVT16240)
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free bus loading
■ Outputs source/sink -32 mA/+64 mA
■ Functionally compatible with the 74 series 16240
■ Latch-up performance exceeds 500 mA
■ ESD performance:
   Human-body model 2000V
   Machine model 200V
   Charged-device model 1000V

简介

74LVT16240属于集成电路（IC）的缓冲器驱动器接收器收发器。由制造生产的74LVT16240缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。