74LVCH16373ADGG中文资料16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state数据手册Nexperia规格书

描述 Description

The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices. When disabled, up to 5.5V can be applied to the outputs. These features allow the use of these devices in mixed 3.3V and 5V applications.
The device consists of two sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are transparent, that is, the latch outputs change each time its corresponding D-input changes. The latches store the information that was present at the D-inputs one set-up time (tsu) preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.

特性 Features

• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power consumption
• Multibyte flow-through standard pinout architecture
• Multiple low inductance supply pins for minimum noise and ground bounce
• Direct interface with TTL levels
• All data inputs have bus hold (74LVCH16373A only)
• High-impedance when VCC = 0 V
• Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V)
• JESD8-5A (2.3 V to 2.7 V)
• JESD8-C/JESD36 (2.7 V to 3.6 V)

• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-B exceeds 200 V
• CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V

• Specified from -40 °C to +85 °C and -40 °C to +125 °C