74LVC377PW数据手册集成电路（IC）的触发器规格书PDF

描述 Description

The 74LVC377 has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). A common clock input (CP) loads all flip-flops simultaneously when data enable input (E) is LOW. The state of each D input, one set-up time before the LOW to HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. Input E must be stable only one set-up time prior to the LOW to HIGH transition for predictable operation.

特性 Features

• Wide supply voltage range from 1.2 V to 3.6 V
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Output drive capability 50 Ω transmission lines at 125 °C
• Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V)
• JESD8-5A (2.3 V to 2.7 V)
• JESD8-C/JESD36 (2.7 V to 3.6 V)

• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-B exceeds 200 V
• CDM JESD22-C101E exceeds 1000 V

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C