OCTAL D-TYPE LATCH HIGH PERFORMANCE

DESCRIPTION The 74LVC373A is a low voltage CMOS OCTAL D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. ■ 5V TOLERANT INPUTS ■ HIGH SPEED: tPD = 6.8ns (MAX.) a

文件：289.2 Kbytes 页数：13 Pages

STMICROELECTRONICS

意法半导体

Package：20-SOIC（0.295"，7.50mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 锁存器 描述：IC LATCH OCTAL D-TYPE 20-SOIC

STMICROELECTRONICS

意法半导体

Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC373A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as t

文件：103.17 Kbytes 页数：12 Pages

PHI

PHI

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

1. General description The 74LVC373A is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change e

文件：274.4 Kbytes 页数：15 Pages

NEXPERIA

安世

OCTAL D-TYPE LATCH HIGH PERFORMANCE

DESCRIPTION The 74LVC373A is a low voltage CMOS OCTAL D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. ■ 5V TOLERANT INPUTS ■ HIGH SPEED: tPD = 6.8ns (MAX.) a

文件：289.2 Kbytes 页数：13 Pages

STMICROELECTRONICS

意法半导体