74LVC30APW中文资料8-input NAND gate数据手册Nexperia规格书

描述 Description

The 74LVC30A is an 8-input NAND gate.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

特性 Features

• Wide supply voltage range from 1.2 V to 3.6 V
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V)
• JESD8-5A (2.3 V to 2.7 V)
• JESD8-C/JESD36 (2.7 V to 3.6 V)

• ESD protection:
• HBM JEDEC JS-001-2012 exceeds 2000 V
• MM JESD22-A115-C exceeds 200 V
• CDM JESD22-C101F exceeds 1000 V

• Specified from ‑40 °C to +85 °C and ‑40 °C to +125 °C