74LVC2G86DP-Q100数据手册集成电路（IC）的门反相器规格书PDF

描述 Description

The 74LVC2G86-Q100 provides a dual 2-input EXCLUSIVE-OR gate.
Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V and 5V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85°C and from -40°C to +125°C

• Wide supply voltage range from 1.65 V to 5.5V
• 5 V tolerant inputs for interfacing with 5 V logic
• High noise immunity
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8B/JESD36 (2.7 V to 3.6V)

• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000V
• HBM JESD22-A114F exceeds 2000V
• MM JESD22-A115-A exceeds 200V (C = 200pF, R = 0Ω)

• ±24 mA output drive (VCC = 3.0 V)
• CMOS low-power consumption
• Latch-up performance exceeds 250mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5V
• Multiple package options