74LVC2G17GV-Q100集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF中文资料

厂商型号	74LVC2G17GV-Q100
参数属性	74LVC2G17GV-Q100 封装/外壳为SC-74，SOT-457；包装为卷带（TR）；类别为集成电路（IC）的缓冲器驱动器接收器收发器；产品描述：IC BUFFER NON-INVERT 5.5V 6TSOP
功能描述	Dual non-inverting Schmitt trigger with 5 V tolerant input
丝印标识	VV
封装外壳	SC-74 / SC-74，SOT-457
文件大小	225.63 Kbytes
页面数量	13 页
生产厂商	Nexperia B.V. All rights reserved
企业简称	NEXPERIA【安世】
中文名称	安世半导体(中国)有限公司官网
原厂标识	NEXPERIA
数据手册	下载地址一下载地址二到原厂下载
更新时间	2025-8-5 17:20:00
人工找货	74LVC2G17GV-Q100价格和库存，欢迎联系客服免费人工找货

1. General description

The 74LVC2G17-Q100 is a dual buffer with Schmitt-trigger inputs. Inputs can be driven from either

3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and

5 V environments.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• Wide supply voltage range from 1.65 V to 5.5 V

• Overvoltage tolerant inputs to 5.5 V

• High noise immunity

• ±24 mA output drive (VCC = 3.0 V)

• CMOS low-power consumption

• Latch-up performance exceeds 250 mA

• Direct interface with TTL levels

• IOFF circuitry provides partial Power-down mode operation

• Complies with JEDEC standard:

• JESD8-7 (1.65 V to 1.95 V)

• JESD8-5 (2.3 V to 2.7 V)

• JESD-8B/JESD36 (2.7 V to 3.6 V)

• ESD protection:

• MIL-STD-883, method 3015 exceeds 2000 V

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

3. Applications

• Wave and pulse shapers for highly noisy environments