74LVC1G02GW-Q100集成电路（IC）的门反相器规格书PDF中文资料

厂商型号	74LVC1G02GW-Q100
参数属性	74LVC1G02GW-Q100 封装/外壳为5-TSSOP，SC-70-5，SOT-353；包装为卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带；类别为集成电路（IC）的门反相器；产品描述：IC GATE NOR 1CH 2-INP 5TSSOP
功能描述	Single 2-input NOR gate
丝印标识	VB
封装外壳	TSSOP5 / 5-TSSOP，SC-70-5，SOT-353
文件大小	231.59 Kbytes
页面数量	12 页
生产厂商	NEXPERIA
中文名称	安世
网址	网址
数据手册	下载地址一下载地址二到原厂下载
更新时间	2025-11-15 18:09:00
人工找货	74LVC1G02GW-Q100价格和库存，欢迎联系客服免费人工找货

1. General description

The 74LVC1G02-Q100 is a single 2-input NOR gate. Inputs can be driven from either 3.3 V or

5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V

environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and

fall times. This device is fully specified for partial power down applications using IOFF. The IOFF

circuitry disables the output, preventing the potentially damaging backflow current through the

device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• Wide supply voltage range from 1.65 V to 5.5 V

• Overvoltage tolerant inputs to 5.5 V

• High noise immunity

• CMOS low power dissipation

• IOFF circuitry provides partial Power-down mode operation

• ±24 mA output drive (VCC = 3.0 V)

• Latch-up performance exceeds 250 mA

• Direct interface with TTL levels

• Complies with JEDEC standard:

• JESD8-7 (1.65 V to 1.95 V)

• JESD8-5 (2.3 V to 2.7 V)

• JESD8C (2.7 V to 3.6 V)

• JESD36 (4.5 V to 5.5 V)

• ESD protection:

• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V