Octal D-type transparent latch 3-State

DESCRIPTION The 74LV373 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT373. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0V to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP

文件：123.2 Kbytes 页数：12 Pages

PHI

PHI

Octal D-type transparent latch 3-State

DESCRIPTION The 74LV373 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT373. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0V to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP

文件：123.2 Kbytes 页数：12 Pages

PHI

PHI

Octal D-type Transparent Latches with 3-state Outputs

Description The HD74LV373A has eight D type latches with three state outputs in a 20 pin package. When the latch enables input is high, the Q outputs will follow the D inputs. When the latch enables goes low, data at the D inputs will be retained at the outputs until latch enable returns high aga

文件：69.25 Kbytes 页数：16 Pages

HITACHIHitachi Semiconductor

日立日立公司

Octal D-type Transparent Latches with 3-state Outputs

Description The HD74LV373A has eight D type latches with three state outputs in a 20 pin package. When the latch enables input is high, the Q outputs will follow the D inputs. When the latch enables goes low, data at the D inputs will be retained at the outputs until latch enable returns high aga

文件：69.25 Kbytes 页数：16 Pages

HITACHIHitachi Semiconductor

日立日立公司

Octal D-type Transparent Latches with 3-state Outputs

Description The HD74LV373A has eight D type latches with three state outputs in a 20 pin package. When the latch enables input is high, the Q outputs will follow the D inputs. When the latch enables goes low, data at the D inputs will be retained at the outputs until latch enable returns high aga

文件：86.37 Kbytes 页数：11 Pages

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