1. General description

The 74LV244 is an 8-bit buffer/line driver with 3-state outputs. The device can be used as two 4-bit

buffers or one 8-bit buffer. The device features two output enables (1OE and 2OE), each controlling

four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance

OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to

interface inputs to voltages in excess VCC.

2. Features and benefits

• Wide supply voltage range from 1.0 to 5.5 V

• CMOS low power dissipation

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Optimized for low voltage applications: 1.0 V to 3.6 V

• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

• Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V; Tamb = 25 °C

• Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V; Tamb = 25 °C

• Complies with JEDEC standards:

• JESD8-7 (1.65 V to 1.95 V)

• JESD8-5 (2.3 V to 2.7 V)

• JESD8C (2.7 V to 3.6 V)

• JESD36 (4.5 V to 5.5 V)

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74LV244D属于集成电路（IC） > 缓冲器，驱动器，接收器，收发器。安世半导体(中国)有限公司制造生产的74LV244D缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。