74LV08APW数据手册集成电路（IC）的门反相器规格书PDF

描述 Description

The 74LV08A is a quad 2-input AND gate.
Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

特性 Features

• Wide supply voltage range from 2.0 V to 5.5 V
• Maximum tpd of 10 ns at 5 V
• Typical VOL(p)< 0.8 V at VCC = 3.3 V, Tamb = 25 °C
• Typical VOH(v)> 2.3 V at VCC = 3.3 V, Tamb = 25 °C
• Supports mixed-mode voltage operation on all ports
• IOFF circuitry provides partial Power-down mode operation
• Latch-up performance exceeds 250 mA per JESD 78 Class II
• ESD protection:
• MM: MM JESD22-A115-B exceeds 200 V
• HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4 kV
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 2 kV

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C