74LS194中文资料SYC数据手册PDF规格书

General Description

This bidirectional shift register is designed to incorporate

virtually all of the features a system designer may want in a

shift register; they feature parallel inputs, parallel outputs,

right-shift and left-shift serial inputs, operating-mode-control

inputs, and a direct overriding clear line. The register

has four distinct modes of operation, namely:

Parallel (broadside) load

Shift right (in the direction QA toward QD)

Shift left (in the direction QD toward QA)

Inhibit clock (do nothing)

Synchronous parallel loading is accomplished by applying

the four bits of data and taking both mode control inputs,

S0 and S1, HIGH. The data is loaded into the associated

flip-flops and appear at the outputs after the positive transition

of the clock input. During loading, serial data flow is

inhibited.

Shift right is accomplished synchronously with the rising

edge of the clock pulse when S0 is HIGH and S1 is LOW.

Serial data for this mode is entered at the shift-right data

input. When S0 is LOW and S1 is HIGH, data shifts left

synchronously and new data is entered at the shift-left

serial input.

Clocking of the flip-flop is inhibited when both mode control

inputs are LOW.

特性 Features

n Parallel inputs and outputs

n Four operating modes:

Synchronous parallel load

Right shift

Left shift

Do nothing

n Positive edge-triggered clocking

n Direct overriding clear