74LS175中文资料安森美半导体数据手册PDF规格书

The LSTTL/MSI SN74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW.

The LS175 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families.

• Edge-Triggered D-Type Inputs

• Buffered-Positive Edge-Triggered Clock

• Clock to Output Delays of 30 ns

• Asynchronous Common Reset

• True and Complement Output

• Input Clamp Diodes Limit High Speed Termination Effects