74LCX125中文资料低压CMOS四路总线缓冲器（3态），5 V容限输入和输出数据手册ST规格书

描述 Description

The 74LCX125 device is a low-voltage CMOS quad bus buffer manufactured with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low-power and high-speed 3.3 V applications and can be interfaced to a 5 V signal environment for both inputs and outputs.

The device requires the 3-state control input G to be set high to place the output in the high impedance state.

It has the same speed performance at 3.3 V as the 5 V AC/ACT family, combined with lower power consumption.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2 kV ESD immunity and transient excess voltage.

特性 Features

• 5 V tolerant inputs and outputs
• High speed
•tPD= 5.2 ns (max.) at VCC= 3 V
• Power-down protection on inputs and outputs
• Symmetrical output impedance
•|IOH| = IOL= 24 mA (min.) at VCC= 3 V
• PCI bus levels guaranteed at 24 mA
• Balanced propagation delay
•tPLH≅ tPHL
• Operating voltage range
•VCC(opr.) = 2.0 V to 3.6 V
• Pin and function compatible with 74 series 125
• Latch-up performance exceeds 500 mA (JESD 17)
• ESD performance
•HBM: 2000 V (MIL STD 883 method 3015)
•MM: 200 V
•CDM: 1000 V

简介

74LCX125属于集成电路（IC）的缓冲器驱动器接收器收发器。由制造生产的74LCX125缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。