74HCT4060DB-Q100数据手册集成电路（IC）的计数器除法器规格书PDF

描述 Description

The 74HC4060-Q100; 74HCT4060-Q100 are high-speed Si-gate CMOS devices thatcomply with JEDEC standard no. 7A. They are pin compatible with Low-power SchottkyTTL (LSTTL).
The 74HC4060-Q100; 74HCT4060-Q100 are 14-stage ripple-carry counter/dividers andoscillators with three oscillator terminals (RS, RTC and CTC), ten buffered outputs (Q3 toQ9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillatorconfiguration allows design of either RC or crystal oscillator circuits. The oscillator may bereplaced by an external clock signal at input RS. In this case keep the other oscillator pins(RTC and CTC) floating. The counter advances on the negative-going transition of RS. AHIGH level on MR resets the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent ofother input conditions. In the HCT version, the MR input is TTL compatible, but the RSinput has CMOS input switching levels and can be driven by a TTL output by using apull-up resistor to VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standardQ100 (Grade 1) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• All active components on chip
• RC or crystal oscillator configuration
• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

• Multiple package options

应用 Application

• Control counters
• Timers
• Frequency dividers
• Time-delay circuits