1. General description

The 74HC4020-Q100; 74HCT4020-Q100 is a 14-stage binary ripple counter with a clock input

(CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0,

and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR

clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter

stage is a static toggle flip-flop. Inputs include clamp diodes. This enables the use of current

limiting resistors to interface inputs to voltages in excess of VCC.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• Wide supply voltage range from 2.0 V to 6.0 V

• CMOS low power dissipation

• High noise immunity

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Complies with JEDEC standards:

• JESD8C (2.7 V to 3.6 V)

• JESD7A (2.0 V to 6.0 V)

• Input levels:

• For 74HC4020-Q100: CMOS level

• For 74HCT4020-Q100: TTL level

• ESD protection:

• MIL-STD-883, method 3015 exceeds 2000 V

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

• Multiple package options

• DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of

solder joints

3. Applications

• Frequency dividing circuits

• Time delay circuits

• Control counters

74HCT4020BQ-Q100属于集成电路（IC） > 计数器，除法器。安世半导体(中国)有限公司制造生产的74HCT4020BQ-Q100计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。