74HCT193D集成电路（IC）的计数器除法器规格书PDF中文资料

74HCT193D属于集成电路（IC）的计数器除法器。由安世半导体(中国)有限公司制造生产的74HCT193D计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。

1. General description

The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down

clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously

with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held

HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will

count down. Only one clock input can be held HIGH at any time to guarantee predictable behavior.

The device can be cleared at any time by the asynchronous master reset input (MR); it may also

be loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up

(TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached

the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go

LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,

the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The

terminal count outputs can be used as the clock input signals to the next higher order circuit in

a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be

fully synchronous, since there is a slight delay time difference added for each stage that is added.

The counter may be preset by the asynchronous parallel load capability of the circuit. Information

present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs

(Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW.

A HIGH level on the master reset (MR) input will disable the parallel load gates, override both

clock inputs and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after

a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a

legitimate signal and will be counted. Inputs include clamp diodes. This enables the use of current

limiting resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

• Wide supply voltage range from 2.0 to 6.0 V

• CMOS low power dissipation

• High noise immunity

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Input levels:

• For 74HC193: CMOS level

• For 74HCT193: TTL level

• Synchronous reversible 4-bit binary counting

• Asynchronous parallel load

• Asynchronous reset

• Expandable without external logic

• Complies with JEDEC standards:

• JESD8C (2.7 V to 3.6 V)

• JESD7A (2.0 V to 6.0 V)

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V.

• Specified from -40 °C to +85 °C and -40 °C to +125 °C.