74HCT166PW中文资料飞利浦数据手册PDF规格书

GENERAL DESCRIPTION

The 74HC/HCT166 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT166 are 8-bit shift registers which have a fully synchronous serial or parallel data entry selected by an active LOW parallel enable (PE) input. When PE is LOW one set-up time prior to the LOW-to-HIGH clock transition, parallel data is entered into the register. When PE is HIGH, data is entered into the internal bit position Q0 from serial data input (Ds), and the remaining bits are shifted one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition.

This feature allows parallel-to-serial converter expansion by tying the Q7 output to the Ds input of the succeeding stage.

FEATURES

• Synchronous parallel-to-serial applications

• Synchronous serial data input for easy expansion

• Clock enable for “do nothing” mode

• Asynchronous master reset

• For asynchronous parallel data load see “165”

• Output capability: standard

• ICC category: MSI