74HC74

Dual D Flip?묯lop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The74HC74isidenticalinpinouttotheLS74.ThedeviceinputsarecompatiblewithstandardCMOSoutputs;withpullupresistors,theyarecompatiblewithLSTTLoutputs. ThisdeviceconsistsoftwoDflip−flopswithindividualSet,Reset,andClockinputs.InformationataD−inputistransferred

74HC74

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERALDESCRIPTION The74HC/HCT74arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES •Outputcapability:standard •ICCcategory:flip-flops

74HC74

Dual D-type flip-flop with set and reset; positive edge-trigger

1.Generaldescription The74HC74and74HCT74aredualpositiveedgetriggeredD-typeflip-flop.Theyhaveindividual data(nD),clock(nCP),set(nSD)andreset(nRD)inputs,andcomplementarynQandnQoutputs. DataatthenD-input,thatmeetstheset-upandholdtimerequirementsontheLOW-

74HC74

High Speed CMOS Logic

74HC74

Dual D-type flip-flop with set and reset; positive edge-trigger

74HC74

High Speed CMOS Logic

74HC74

Dual D-type flip-flop with set and reset; positive edge-trigger

Generaldescription The74HC74and74HCT74aredualpositiveedgetriggeredD-typeflip-flop.Theyhaveindividualdata(nD),clock(nCP),set(nSD)andreset(nRD)inputs,andcomplementarynQandnQoutputs.DataatthenD-input,thatmeetstheset-upandholdtimerequirementsontheLOW-to-HI

74HC74

Dual D-type flip-flop with set and reset; positive edge-trigger

Generaldescription The74HC74and74HCT74aredualpositiveedgetriggeredD-typeflip-flop.Theyhaveindividualdata(nD),clock(nCP),set(nSD)andreset(nRD)inputs,andcomplementarynQandnQoutputs.DataatthenD-input,thatmeetstheset-upandholdtimerequirementsontheLOW-to-HI

74HC74A

Dual D Flip-Flop with Set and Reset

74HC74AF

Dual D-Type Flip Flop Preset and Clear

Features •Highspeed:fmax=77MHz(typ.)atVCC=5V •Lowpowerdissipation:ICC=2µA(max)atTa=25°C •Highnoiseimmunity:VNIH=VNIL=28VCC(min) •Outputdrivecapability:10LSTTLloads •Symmetricaloutputimpedance:|IOH|=IOL=4mA(min) •Balancedpropagationdelays: