丝印：74HC595；Package：SO16；8-bit shift register with output latches (3-state)

Description The M74HC595 device is a high speed CMOS 8-bit shift register with output latches (3-state) fabricated with silicon gate C2MOS technology. This device contains an 8-bit serial in, parallel out shift register that feeds an 8-bit D-type storage register. The storage register has 8

文件：579.68 Kbytes 页数：22 Pages

STMICROELECTRONICS

意法半导体

丝印：74HC595D；Package：SOIC16；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • 8-Bit Shift Register/Latch (3-state) General The 74HC595D is a high speed 8-BIT SHIFT REGISTER/LATCH fabricated with silicon gate C2MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The 7

文件：271.76 Kbytes 页数：17 Pages

TOSHIBA

东芝

丝印：74HC595Y；Package：SO16；8-bit shift register with output latches (3-state)

Description The M74HC595 device is a high speed CMOS 8-bit shift register with output latches (3-state) fabricated with silicon gate C2MOS technology. This device contains an 8-bit serial in, parallel out shift register that feeds an 8-bit D-type storage register. The storage register has 8

文件：579.68 Kbytes 页数：22 Pages

STMICROELECTRONICS

意法半导体

丝印：74HC595D；Package：SOIC16；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • 8-Bit Shift Register/Latch (3-state) General The 74HC595D is a high speed 8-BIT SHIFT REGISTER/LATCH fabricated with silicon gate C2MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The 7

文件：271.76 Kbytes 页数：17 Pages

TOSHIBA

东芝

8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs

8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs The MC74HC595A consists of an 8−bit shift register and an 8−bit D−type latch with three−state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also pro

文件：248.98 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

DESCRIPTION The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The shift regi

文件：140.7 Kbytes 页数：28 Pages

PHI

飞利浦

8 BIT SHIFT REGISTER WITH OUTPUT LATCHES 3 STATE

DESCRIPTION The M54/74HC595 is a high speed CMOS 8-BIT SHIFT REGISTERS/OUTPUT LATCHES (3-STATE) fabricated in silicon C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device contains an 8-bit serial-in, parallel-out shift regist

文件：282.9 Kbytes 页数：13 Pages

STMICROELECTRONICS

意法半导体

8-bit Shift Register/Latch (with 3-state outputs)

Description This device each contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-

文件：57.87 Kbytes 页数：10 Pages

HitachiHitachi Semiconductor

日立日立公司

8?묪it Serial?묲nput/Serial or Parallel?뭀utput Shift Register with Latched 3?뭆tate Outputs

The 74HC595 consists of an 8−bit shift register and an 8−bit D−type latch with three−state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8−bit latch. The shift register and latch have independent clock i

文件：160.83 Kbytes 页数：13 Pages

ONSEMI

安森美半导体

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

1. General description The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading a

文件：327.56 Kbytes 页数：21 Pages

NEXPERIA

安世