1. General description

The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device

features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs

enter the latches. In this condition the latches are transparent, a latch output will change each time

its corresponding D-input changes. When LE is LOW the latches store the information that was

present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE

causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not

affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting

resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

• Wide supply voltage range from 2.0 to 6.0 V

• CMOS low power dissipation

• High noise immunity

• Input levels:

• For 74HC573: CMOS level

• For 74HCT573: TTL level

• Inputs and outputs on opposite sides of package allowing easy interface with microprocessors

• Useful as input or output port for microprocessors and microcomputers

• 3-state non-inverting outputs for bus-oriented applications

• Common 3-state output enable input

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Complies with JEDEC standards:

• JESD8C (2.7 V to 3.6 V)

• JESD7A (2.0 V to 6.0 V)

• ESD protection:

• • HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• Multiple package options

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74HC573BQ属于集成电路（IC） > 锁存器。安世半导体(中国)有限公司制造生产的74HC573BQ锁存器锁存器是类似于触发器的基本数字存储设备，但是不同之处在于，在锁存使能（或类似命名）信号处于有效逻辑状态的任何时间，保持的逻辑状态都可以改变。“透明”锁存器还允许设备输出在锁存使能信号有效时反映输入的当前状态，而相反的是，状态仅在保持状态已固定时改变。