74HC4520PW中文资料Dual 4-bit synchronous binary counter数据手册Nexperia规格书

描述 Description

The 74HC4520; 74HCT4520 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR). The counter advances on the LOW-to-HIGH transition of nCP0 when nCP1 is HIGH. It also advances on the HIGH-to-LOW transition of nCP1 when nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter. The other clock input may be used as a clock enable input. A HIGH on nMR, resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

特性 Features

• Complies with JEDEC standard no. 7A
• Input levels:
• For 74HC4520: CMOS level
• For 74HCT4520: TTL level

• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V

• Specified from -40 °C to +85 °C and -40 °C to +125 °C

应用 Application

• Multistage synchronous counting
• Multistage asynchronous counting
• Frequency dividers