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74HC4053BQ-Q100数据手册Nexperia中文资料规格书

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厂商型号

74HC4053BQ-Q100

功能描述

Triple 2-channel analog multiplexer/demultiplexer

制造商

Nexperia Nexperia B.V. All rights reserved

中文名称

安世 安世半导体(中国)有限公司

数据手册

下载地址下载地址二

更新时间

2025-8-9 23:00:00

人工找货

74HC4053BQ-Q100价格和库存,欢迎联系客服免费人工找货

74HC4053BQ-Q100规格书详情

描述 Description

The 74HC4053-Q100; 74HCT4053-Q100 is a triple single-pole double-throw analog switch (3x SPDT) suitable for use in analog or digital 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). A digital enable input (E) is common to all switches. When E is HIGH, the switches are turned off. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• Wide analog input voltage range from -5 V to +5 V
• Low ON resistance:
• 80 Ω (typical) at VCC - VEE = 4.5 V
• 70 Ω (typical) at VCC - VEE = 6.0 V
• 60 Ω (typical) at VCC - VEE = 9.0 V

• Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals
• Typical ‘break before make’ built-in
• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
• CDM AEC-Q100-011 revision B exceeds 1000 V

• Multiple package options
• DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints

应用 Application

• Analog multiplexing and demultiplexing
• Digital multiplexing and demultiplexing
• Signal gating

技术参数

  • 制造商编号

    :74HC4053BQ-Q100

  • 生产厂家

    :Nexperia

  • Configuration

    :SPDT-Z

  • VCC (V)

    :2.0 - 10.0

  • RON (Ω)

    :200

  • Logic switching levels

    :CMOS

  • Output drive capability (mA)

    :± 5.2

  • tpd (ns)

    :12

  • Power dissipation considerations

    :very low

  • Tamb (°C)

    :-40~125

  • Rth(j-a) (K/W)

    :89

  • Ψth(j-top) (K/W)

    :10.8

  • Rth(j-c) (K/W)

    :57

  • Package name

    :DHVQFN16

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