74HC4040DB中文资料74HC4040DB - 12-stage binary ripple counter 数据手册Nexperia规格书

描述 Description

12-stage binary ripple counter - The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

特性 Features

·Complies with JEDEC standard no. 7A
·Input levels:·For 74HC4040: CMOS level
·For 74HCT4040: TTL level

应用 Application

·Frequency dividing circuits
·Time delay circuits
·Control counters