1. General description

The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded outputs

(Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs (CP0 and CP1)

and an overriding asynchronous master reset input (MR). The counter is advanced by either a

LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0

is HIGH. When cascading counters, the Q5-9 output, which is LOW while the counter is in states

5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the

counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and

CP1). Automatic code correction of the counter is provided by an internal circuit: following any

illegal code the counter returns to a proper counting mode within 11 clock pulses. Inputs include

clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in

excess of VCC.

2. Features and benefits

• Wide supply voltage range from 2.0 V to 6.0 V

• CMOS low power dissipation

• High noise immunity

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Complies with JEDEC standards:

• JESD8C (2.7 V to 3.6 V)

• JESD7A (2.0 V to 6.0 V)

• Input levels:

• For 74HC4017: CMOS level

• For 74HCT4017: TTL level

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• Multiple package options

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74HC4017PW属于集成电路（IC） > 计数器，除法器。安世半导体(中国)有限公司制造生产的74HC4017PW计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。