74HC377PW-Q100数据手册集成电路（IC）的触发器规格书PDF

描述 Description

The 74HC377‑Q100; 74HCT377‑Q100 is an octal positive‑edge triggered D‑type flip‑flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW‑to‑HIGH clock (CP) transition. Input E must be stable one set-up time prior to the LOW‑to‑HIGH transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40°C to +85°C and from -40°C to +125°C

• Input levels:
• For 74HC377-Q100: CMOS level
• For 74HCT377-Q100: TTL level

• Common clock and master reset
• Eight positive edge-triggered D-type flip-flops
• Complies with JEDEC standard no. 7A
• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000V
• HBM JESD22-A114F exceeds 2000V
• MM JESD22-A115-A exceeds 200V (C = 200pF, R = 0Ω)

• Multiple package options