74HC373PW数据手册集成电路（IC）的锁存器规格书PDF

描述 Description

The 74HC373; 74HCT373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

特性 Features

• Input levels:
• For 74HC373: CMOS level
• For 74HCT373: TTL level

• 3-state non-inverting outputs for bus oriented applications
• Common 3-state output enable input
• Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573
• Complies with JEDEC standard no. 7 A
• ESD protection:
• HBM JESD22-A114F exceeds 2 000 V
• MM JESD22-A115-A exceeds 200 V

• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C