74HC373PW集成电路（IC）的锁存器规格书PDF中文资料

厂商型号	74HC373PW
参数属性	74HC373PW 封装/外壳为20-TSSOP（0.173"，4.40mm 宽）；包装为卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带；类别为集成电路（IC）的锁存器；产品描述：IC OCTAL D TRANSP LATCH 20TSSOP
功能描述	Octal D-type transparent latch; 3-state
封装外壳	20-TSSOP（0.173"，4.40mm 宽）
文件大小	282.05 Kbytes
页面数量	16 页
生产厂商	Nexperia B.V. All rights reserved
企业简称	NEXPERIA【安世】
中文名称	安世半导体(中国)有限公司官网
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数据手册	下载地址一下载地址二到原厂下载
更新时间	2025-6-27 22:59:00
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1. General description

The 74HC373; 74HCT373 is an octal D-type transparent latch with 3-state outputs. The device

features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs

enter the latches. In this condition the latches are transparent, a latch output will change each time

its corresponding D-input changes. When LE is LOW the latches store the information that was

present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE

causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not

affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting

resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

• Wide supply voltage range from 2.0 V to 6.0 V

• CMOS low power dissipation

• High noise immunity

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Complies with JEDEC standards:

• JESD8C (2.7 V to 3.6 V)

• JESD7A (2.0 V to 6.0 V)

• Input levels:

• For 74HC373: CMOS level

• For 74HCT373: TTL level

• 3-state non-inverting outputs for bus oriented applications

• Common 3-state output enable input

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• Multiple package options

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C