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74HC193DB-Q100中文资料74HC193DB-Q100 - Presettable synchronous 4-bit binary up/down counter 数据手册Nexperia规格书

厂商型号 |
74HC193DB-Q100 |
参数属性 | 74HC193DB-Q100 封装/外壳为16-SSOP(0.209",5.30mm 宽);包装为卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带;类别为集成电路(IC)的计数器除法器;产品描述:IC COUNTER U/D 4BIT BIN 16SSOP |
功能描述 | 74HC193DB-Q100 - Presettable synchronous 4-bit binary up/down counter |
封装外壳 | 16-SSOP(0.209",5.30mm 宽) |
制造商 | Nexperia Nexperia B.V. All rights reserved |
中文名称 | 安世 安世半导体(中国)有限公司 |
数据手册 | |
更新时间 | 2025-9-23 11:16:00 |
人工找货 | 74HC193DB-Q100价格和库存,欢迎联系客服免费人工找货 |
74HC193DB-Q100规格书详情
描述 Description
Presettable synchronous 4-bit binary up/down counter - The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device counts up. If the CPD clock is pulsed while CPU is held HIGH, the device counts down. Only one clock input can be held HIGH at any time to guarantee predictable behavior. The device can be cleared at any time by the asynchronous master reset input (MR). It may also be loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU causes TCU to go LOW. TCU remains LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the TCD output goes LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs duplicate the clock waveforms and can be used as the clock input signals to the next higher-order circuit in a multistage counter. Multistage counters are not fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information on the parallel data inputs (D0 to D3), is loaded into the counter. This information appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input disables the parallel load gates. It overrides both clock inputs and sets all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock is interpreted as a legitimate signal and it is counted. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
特性 Features
·Automotive product qualification in accordance with AEC-Q100 (Grade 1)·Specified from -40 °C to +85 °C and from -40 °C to +125 °C
技术参数
- 制造商编号
:74HC193DB-Q100
- 生产厂家
:Nexperia
- Product status
:Production
- V_CC (V)
:2.0 - 6.0
- Output drive capability (mA)
:+/- 5.2
- Logic switching levels
:CMOS
- t_pd (ns)
:20
- f_max (MHz)
:41
- Power dissipation considerations
:low
- T_amb (Cel)
:-40~125
- R_th(j-a) (K/W)
:148
- Ψ_th(j-top) (K/W)
:42.0
- Package name
:SSOP16
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
Nexperia(安世) |
24+ |
SSOP16208mil |
2886 |
原装现货,免费供样,技术支持,原厂对接 |
询价 | ||
HARRIS/哈里斯 |
23+ |
5000 |
原厂授权代理,海外优势订货渠道。可提供大量库存,详 |
询价 | |||
ti |
24+ |
N/A |
6980 |
原装现货,可开13%税票 |
询价 | ||
24+ |
N/A |
62000 |
一级代理-主营优势-实惠价格-不悔选择 |
询价 | |||
MAXIM/美信 |
23+ |
SOT23-5 |
69820 |
终端可以免费供样,支持BOM配单! |
询价 | ||
NEXPERIA/安世 |
2447 |
SOT338-1 |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
询价 | ||
Nexperia |
25+ |
电联咨询 |
7800 |
公司现货,提供拆样技术支持 |
询价 | ||
NEXPERIA/安世 |
22+ |
SOT338-1 |
10990 |
原装正品 |
询价 | ||
恩XP |
22+ |
16SSOP |
9000 |
原厂渠道,现货配单 |
询价 | ||
TI |
24+ |
SOP16 |
56800 |
特价现货,下单送华为手机.香港 日本 新加坡 |
询价 |