74HC164中文资料8-bit Parallel-out Serial Shift Registers数据手册ETEK规格书

描述 Description

These 8-bit shift registers feature AND-gated serial inputs and an asynchronous /clear input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

特性 Features

• AND-Gated (Enable/Disable) Serial Inputs

• Fully Buffered Clock and Serial Inputs

• Direct Clear

• Product name and package

应用 Application

• Memory chip select decoding
• Data transmission system