74HC138PW集成电路（IC）的信号开关多路复用器解码器规格书PDF中文资料

厂商型号	74HC138PW
参数属性	74HC138PW 封装/外壳为16-TSSOP（0.173"，4.40mm 宽）；包装为卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带；类别为集成电路（IC）的信号开关多路复用器解码器；产品描述：IC DECODER/DEMUX 1X3:8 16TSSOP
功能描述	3-to-8 line decoder/demultiplexer; inverting
封装外壳	16-TSSOP（0.173"，4.40mm 宽）
文件大小	274.63 Kbytes
页面数量	15 页
生产厂商	Nexperia B.V. All rights reserved
企业简称	NEXPERIA【安世】
中文名称	安世半导体(中国)有限公司官网
原厂标识
数据手册	下载地址一下载地址二到原厂下载
更新时间	2025-6-28 22:59:00
人工找货	74HC138PW价格和库存，欢迎联系客服免费人工找货

1. General description

The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to

eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and

E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable

function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '138 ICs

and one inverter. The '138 can be used as an eight output demultiplexer by using one of the active

LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include

clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in

excess of VCC.

2. Features and benefits

• Wide supply voltage range from 2.0 to 6.0 V

• CMOS low power dissipation

• High noise immunity

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Demultiplexing capability

• Multiple input enable for easy expansion

• Ideal for memory chip select decoding

• Active LOW mutually exclusive outputs

• Input levels:

• For 74HC138: CMOS level

• For 74HCT138: TTL level

• Complies with JEDEC standards:

• JESD8C (2.7 V to 3.6 V)

• JESD7A (2.0 V to 6.0 V)

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• Multiple package options

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C